1. Field of the Invention
This invention pertains in general to shallow trench isolations in a semiconductor device and, more particularly, to a method of forming substantially planar shallow trench isolations.
2. Description of the Related Art
Shallow trench isolations ("STIs") are used for device isolation in an integrated circuit. A conventional process of forming STIs begins by defining a wafer substrate. An insulating layer of silicon dioxide is then grown over the substrate, followed by depositing a layer of silicon nitride over the insulating layer. After shallow trenches are patterned and formed in the device substrate and through the insulating layer and the silicon nitride layer, silicon dioxide is deposited, filling the trenches and in the process forming a layer over the silicon nitride layer. Silicon dioxide deposited over the silicon nitride layer is removed, usually with chemicalmechanical polishing ("CMP"), to obtain a substantially planar surface.
However, the silicon dioxide layer, deposited by a conventional low pressure chemical vapor deposition ("LPCVD") technique, is often thicker at the wafer edge, or "bowl-shaped." As a result, the CMP process that leaves a substantially planar surface would also leave silicon dioxide residues over the silicon nitride layer at the wafer edge. If the residues are not removed, they act as a mask and prevent subsequent removal of the silicon nitride layer. If, however, the wafer is intentionally over-polished during the CMP process to remove the silicon dioxide at the wafer edge, the STIs closer to the center of the wafer will become bowl-shaped, i.e., nonplanar, which may impede subsequent STI formation process steps.
The process continues by etching back the silicon dioxide in the trenches using a buffered oxide etch ("BOE"), a type of isotropic etching, to yield a planar surface. The silicon nitride layer serves as an etch stop for the BOE. This is followed by the removal of the silicon nitride layer with hot phosphoric acid H.sub.3 PO.sub.4.
This conventional STI formation process, however, often leaves microtrenches that result in nonplanarity of the oxide surface, at the interface between the silicon dioxide in the trenches and the device substrate. The micro-trenches present an impediment to subsequent device formation processes. The formation of microtrenches is largely due to the BOE that leaves undesired micro-trenches between the etched material and etch-stop. When the etch-stop, i.e., silicon nitride, is stripped, the micro-trenches remain.
FIG. 1 illustrates the resulting structure. Referring to FIG. 1, micro-trenches 2 are formed at the interface between silicon substrate 4 and silicon dioxide 6 in shallow trenches 8.